The fetch-decode-execute cycle is the repeated process through which the central processing unit (CPU) retrieves a program instruction from memory, interprets it, and carries it out. The cycle continues while a program runs.
How the cycle works
The CPU uses registers, the control unit (CU), the arithmetic logic unit (ALU), and system buses to process each instruction.
| Stage | What happens |
|---|---|
| Fetch | The address of the next instruction is copied from the program counter (PC) to the memory address register (MAR). The instruction at that address travels from memory through the data bus into the memory data register (MDR), then moves to the current instruction register (CIR). The PC is incremented so that it identifies the next instruction. |
| Decode | The control unit interprets the instruction in the CIR. It identifies the opcode, which specifies the operation, and any operand, which identifies the data or address involved. |
| Execute | The control unit sends control signals to the required components. The ALU might perform a calculation or comparison, data might be transferred, or the PC might be changed by a branch instruction. The result may be stored in a register or memory. |
The stages are coordinated by the system clock. The address bus carries memory addresses, the data bus carries instructions and data, and the control bus carries signals such as memory-read or memory-write commands.
A common misconception is that one clock pulse completes an entire instruction. In reality, an instruction normally requires multiple clock cycles because several register transfers and control signals are needed.
Exam technique
For an IB question using describe or explain, give the stages in order and state how the PC, MAR, MDR, and CIR are used. Do not merely write “fetch, decode, execute”; examiners expect the movement of the instruction and the roles of the control unit and relevant registers.
