The instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), and accumulator (ACC) are CPU registers with distinct contents and purposes. Together, they coordinate instruction processing in the fetch-decode-execute cycle.
| Register | What it stores | Role |
|---|---|---|
| Instruction register (IR) | Current instruction | Holds it while the control unit decodes and executes it. |
| Program counter (PC) | Address of the next instruction | Identifies the next instruction; normally increments after fetching unless a branch changes it. |
| Memory address register (MAR) | Memory address | Specifies the location to read from or write to. |
| Memory data register (MDR) | Transferred data or instruction | Buffers information moving between the CPU and memory. |
| Accumulator (ACC) | Intermediate ALU result | Holds operands and arithmetic or logical results in a simplified CPU model. |
During the fetch stage, the address in the PC is copied to the MAR. The instruction at that address is read from memory into the MDR, then copied into the IR. The PC is normally incremented to identify the next instruction; a branch may instead replace its value.
The control unit decodes the instruction in the IR. During execution, the MAR and MDR may be reused for memory access, while the ACC can hold a value being processed by the arithmetic logic unit (ALU).
A common misconception is that the MAR stores data. It does not: the MAR stores an address, whereas the MDR stores the contents transferred to or from that address.
Exam technique
For an IB distinguish question, state both what each register stores and what it does. In a fetch trace, write PC to MAR, memory to MDR, and MDR to IR, then state that the PC is updated. Do not claim that the PC always increases: branch instructions can load a different address.
