The CPU transfers instructions and data between main memory and its registers through three buses. During the fetch-decode-execute cycle, the control unit (CU) coordinates these transfers in a fixed sequence.
Bus functions
| Bus | Function |
|---|---|
| Address bus | Carries a memory address from the memory address register to memory; normally unidirectional. |
| Data bus | Carries instructions and data between memory and the memory data register; bidirectional. |
| Control bus | Carries signals such as memory read, memory write and timing signals. |
Fetch
- The program counter (PC) holds the address of the next instruction. This address is copied to the memory address register (MAR).
- The MAR sends the address along the address bus. The CU sends a memory-read signal along the control bus.
- Memory sends the instruction along the data bus to the memory data register (MDR).
- The instruction moves from the MDR to the current instruction register (CIR). The PC is incremented to address the next instruction.
Decode and execute
During decode, the CU interprets the instruction held in the CIR, identifying its operation and operand. If another memory value is needed, its address enters the MAR; the value then returns through the data bus into the MDR.
During execute, the CU sends control signals to the relevant components. The arithmetic logic unit (ALU) may process register values and store the result in the accumulator (ACC). A result written to memory passes through the MDR and data bus, with its destination address in the MAR.
A common misconception is that registers communicate directly with memory. Instead, the MAR and MDR provide the memory interface, while the buses carry addresses, values and control signals.
Exam technique
For an IB explain question on A1.1 computer hardware and operation, present the cycle chronologically. Name each register, state what it holds, and identify the bus used for every transfer; simply listing definitions does not explain the interaction.
