The Fetch, Decode, and Execute Cycle
- The Fetch Decode Execute cycle is the basic set of steps the CPU repeats to run any instruction.
- This process is synchronised by the clock, the component that keeps everything ticking in time.
What is the Clock?
- The clock is a tiny circuit that sends out regular electrical pulses.
- Each pulse = one clock cycle.
- The CPU uses these pulses to time its operations, every stage of the FDE cycle happens in sync with the clock.
- Clock speed is measured in Hertz (Hz) e.g. 3GHz = 3 billion cycles per second.
“More clock speed = always faster.”
However, this is not always the case: other factors like cache, instruction type, and core architecture also matter.
Faster clock = more instructions processed per second, but also more heat and power usage.
The clock is like a metronome in an orchestra, it keeps everything moving at the same pace, beat by beat.
Overview of the Fetch, Decode, and Execute Cycle
- The fetch, decode, and execute cycle is the fundamental process by which a CPU executes instructions.
- It consists of three main phases:
- Fetch: Retrieve the instruction from memory.
- Decode: Interpret the instruction.
- Execute: Perform the operation specified by the instruction.
The speed and efficiency of a CPU are largely determined by how quickly it can complete this cycle.
Fetch Phase: Retrieving Instructions
- Program Counter (PC): Holds the address of the next instruction to be executed.
- Memory Address Register (MAR): Receives the address from the PC.
- Control Unit: sends a signal on the control bus to "read".
- The address bus carries the address from the MAR, the control bus carries the signal to "read" and the data or instruction at the specified location is then returned from memory to the CPU on the data bus.
- Memory Data Register (MDR): Temporarily holds the fetched instruction.
- Instruction Register (IR): Stores the instruction for decoding.
- This whole process is timed by the clock, fetch happens on one or more cycles.
The address bus carries the memory address from the MAR to the memory, while the data bus transfers the instruction from memory to the MDR.
CPU Instruction Set
The instruction set is the collection of basic machine-level commands that a CPU is designed to understand and execute. such as load, store, add, compare, and jump.
It forms the CPU’s vocabulary and defines what operations it can perform.
Decode Phase: Interpreting the Instruction
- Control Unit (CU): Reads the instruction from the IR.
- Decodes it: According to the CPU Instruction Set
- Opcode: Determines the operation to be performed (e.g., ADD, SUB).
- Operands: Identify the data to be used or manipulated.
- Addressing Modes: Specify how to locate the operands (e.g., direct, indirect).
The control bus carries signals to coordinate the decoding process, ensuring that the correct components are activated.
Execute Phase: Performing the Operation
- Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
- Memory Access: Load or store data between registers and memory.
- Control Operations: Alter the flow of execution (e.g., jumps, branches).
- Result: Result may be stored in a register (Accumulator), written to memory, or used to update the PC.
The control bus manages signals for read/write operations, while the data bus transfers data between the CPU and memory.
Interaction Between Memory and Registers
- Address Bus: Carries memory addresses from the CPU to memory.
- Data Bus: Transfers data and instructions between the CPU and memory.
- Control Bus: Manages control signals for read/write operations and synchronization.
The width of the data bus determines how much data can be transferred in a single operation, while the address bus limits the maximum addressable memory.
Executing an ADD Instruction
- Fetch:
- PC points to the address of the ADD instruction.
- Instruction is fetched from memory and stored in the IR.
- Decode:
- CU decodes the instruction, identifying the opcode (ADD) and operands (e.g., R1, R2).
- Execute:
- ALU adds the values in R1 and R2.
- Result is stored in the destination register (e.g., R3).
The fetch, decode, and execute cycle is a continuous loop, with the PC incrementing after each instruction to point to the next one.
Significance of the Fetch, Decode, and Execute Cycle
- Efficiency: The cycle's speed directly impacts the CPU's performance.
- Scalability: Modern CPUs use techniques like pipelining to overlap stages and improve throughput.
- Universality: The cycle is a fundamental pattern used in all modern processors, from simple microcontrollers to complex multi-core CPUs.
- When analyzing the fetch, decode, and execute cycle, pay close attention to the role of each register and bus.
- Understanding their interactions is key to mastering CPU operations.
- Can you describe each stage of the Fetch Decode Execute cycle?
- Can you understand how the CPU clock controls the timing of operations?
- Can you explain what a clock cycle is and how it affects performance?
- Can you explain how the Program Counter, registers, and buses interact?
- Can you explain the purpose of the clock, ALU, and CU?
