IB Computer Science Topic A1.1.4: Purposes of Different Types of Primary Memory Notes

Primary Memory: The Four Stores the CPU Can Reach Directly

1. Primary memory is memory the CPU can address directly, holding what is needed right now rather than what might be needed later.
2. The syllabus names four types: RAM, ROM, cache and registers.
3. One rule runs through all of them: the closer a store sits to the CPU, the faster and smaller it is, and the more it costs per bit.

The Hierarchy, Fastest First

1. Each step down the table is slower to reach, larger in capacity and cheaper per bit than the one above it.
2. ROM sits outside the speed ladder: it is there because the machine needs instructions available before RAM has anything in it.
3. Secondary storage such as an SSD or hard drive sits below RAM again and is not primary memory, because the CPU cannot address it directly.

Random-Access Memory (RAM): The Working Space

1. RAM is volatile, so everything in it is lost the moment power goes.
2. The CPU can both read from it and write to it, and can reach any address in about the same time, which is what "random access" means.
3. It holds the operating system, every running program and the data those programs are working on.
4. When RAM runs out, the operating system moves less-used pages to secondary storage, and the machine slows dramatically because that store is orders of magnitude slower.

DRAM and SRAM

1. Dynamic RAM (DRAM)
   1. Stores each bit as a charge that leaks away, so it has to be refreshed thousands of times a second.
   2. Cheap and dense, which is why it is used for main memory.
2. Static RAM (SRAM)
   1. Holds each bit in a latch, so it needs no refresh and responds faster.
   2. Uses several transistors per bit, so it is expensive and low density, which is why it is reserved for cache.

Read-Only Memory (ROM): What Runs Before Anything Is Loaded

1. ROM is non-volatile, so its contents survive with the power off.
2. It holds the firmware, the BIOS or UEFI code that initialises the hardware and then loads the operating system from secondary storage.
3. Its contents are written once at manufacture and are not changed during normal operation.
4. Embedded systems such as a microwave or a printer keep their whole control program in ROM, since it never needs to change.

Cache: Three Levels Between the Core and RAM

1. L1 Cache
   1. Smallest and fastest, built into each core, holding the data and instructions that core touched most recently.
2. L2 Cache
   1. Larger and slightly slower, either dedicated to one core or shared by a small group.
3. L3 Cache
   1. Largest and slowest of the three, shared by every core, which also lets cores see each other's recent data.
4. Cache is built from SRAM and is volatile, exactly like RAM, but sits far closer to the core.

Cache Hits and Cache Misses: Where the Speed Actually Comes From

1. Cache hit
   1. The CPU finds what it asked for in the cache and gets it back in a few clock cycles.
2. Cache miss
   1. The data is not there, so the CPU has to go out to RAM, which takes hundreds of cycles instead.
   2. It brings back a whole block of neighbouring addresses rather than the single value, on the bet that the next request will be nearby.
3. The measure that matters is the hit rate, the share of requests answered from cache.

How the CPU Keeps the Hit Rate High

1. Prefetching
   1. The CPU predicts what will be needed next, usually the following block in a sequence, and loads it before the request arrives.
2. Replacement policies
   1. When the cache is full, something has to be evicted to make room.
   2. Least Recently Used evicts whatever has gone longest without being touched; First-In-First-Out simply evicts the oldest arrival.
3. Locality
   1. Both tricks work only because real programs reuse the same data and step through memory in order, which is why a loop over an array is so much faster than the same work done in random order.

Registers: The Fastest Store of All

1. Registers sit inside the CPU itself, so the ALU reads them with no memory access at all.
2. Each one holds a single value of 32 or 64 bits, and a CPU has only a few dozen of them.
3. They are volatile, and they hold the instruction, the addresses and the intermediate values in use at this instant.
4. The named registers you need, the IR, PC, MAR, MDR and AC, and what each one does, are covered in A1.1.1.